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Friday, October 29 • 12:00pm - 1:00pm
C++20 on Xilinx FPGA with SYCL for Vitis

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FPGA (Field-Programmable Gate Arrays) are electronic devices which are
programmable with a configuration memory to implement arbitrary
electronic circuits. While they have been used for decades to
implement various adaptable electronic components, they got some
traction more recently to be used as generic programmable accelerators
more suitable for software programmers.

There are already HLS (High-Level Synthesis) tools to translate some
functions written with languages like C/C++ into equivalent electronic
circuits which can be called from programs running on processors to
accelerate parts of a global application, often in an energy-efficient
way. The current limitation is that there are 2 different programs:
the host part, running the main application, and the device part,
glued together with an interface library without any type-safety

Since the C++ standard does not address yet the concept of hardware
heterogeneity and remote memory, the Khronos Group organization has
developed SYCL, an open standard defining an executable DSL
(Domain-Specific Language) using pure modern C++ without any
extension. There are around 10 different SYCL implementations
targeting various devices allowing a single-source C++ application to
run on CPU and controlling various accelerators (CPU, GPU, DSP, AI...)
in a unified way by using different backends at the same time in a
single type-safe C++ program.

We present a SYCL implementation https://github.com/triSYCL/sycl
targeting Xilinx Alveo FPGA cards by merging 2 different open-source
implementations, Intel’s oneAPI DPC++ with some LLVM passes from

For a C++ audience, this presentation gives a concrete example on why
the C++ standard does not describe detailed execution semantics
(stack, cache, registers...): because C++ can be executed on devices
which are not even processors.

While this presentation targets FPGA and a SYCL implementation from a
specific vendor, the content provides also:
- a generic introduction to FPGA which should be interesting outside
of Xilinx or even without the use of SYCL;
- how C++ can be translated in some equivalent electronic circuits;
- a generic introduction to SYCL which should be interesting for
people interested to know more about heterogeneous programming and
C++, beyond only FPGA.

ALL TALK SESSIONS CAN BE ACCESSED FROM THE MAIN LOBBY: https://cppcon.digital-medium.co.uk/

avatar for Ronan Keryell

Ronan Keryell

Principal Software Engineer, Xilinx
Ronan Keryell is principal software engineer at Xilinx Research Labs,where he works on high-level programming models for heterogeneoussystems, such as FPGA and CGRA, with the open-sourcehttps://github.com/triSYCL/triSYCL SYCL implementation.He is the specification editor of the SYCL... Read More →

Friday October 29, 2021 12:00pm - 1:00pm MDT
Online A